1. Field of the Invention
This invention relates to an improved method and arrangement for transferring data within a memory or between different memories.
2. Description of the Prior Art
In data processing equipment, either the central processing unit (CPU), or a direct memory access controller (DMAC) controls reading and writing data into memory.
FIG. 1 shows a circuit in which a CPU 11 directly controls a memory 12. While writing data, the CPU 11 places a control line 13 in a write state and uses an address bus 14 to specify an address of a memory location into which data are to be written. A data bus 15, which is eight bits wide in this example, is used to transfer data into the memory 12.
FIG. 2 shows a circuit with a DMAC 16 controlling a memory. The circuit in FIG. 2 is an improvement over that in FIG. 1 since the DMAC decreases the load on the CPU.
FIG. 3 illustrates an arrangement of a memory 12. In the examples shown in FIGS. 1-4, it is assumed that the memory 12 address are ten bits long and data are stored in eight bit memory words. The memory 12 has a word-organized memory cell assembly 21 in which memory cells are arranged in a matrix form of 128 rows.times.8 columns.times.8 bits/column. Memory assembly 21 is considered to be word-organized since each memory location, specified by a unique row and column number, contains a word, in this case of eight bits. A row or line decoder 22 receives the seven most significant bits of the address, bits A3 . . . A9, to select one of the 128 linear rows. When a linear row is selected, assembly 21 outputs all 64 bits in that row. These bits are then fed into eight column decoders 23, each corresponding to a different bit of the word to be stored.
Each of the eight column decoders 23 receives the three least significant bits of the address, bits A.sub.0, A.sub.1, A.sub.2, to select one out of the eight columns. The outputs from column decoders 23 are connected to lines D.sub.0 through D.sub.7 of data bus 15. When memory 12 receives a 10 bit address, it identifies the eight bit word selected by that address and transmits it to data bus 15. Lines D.sub.0 -D.sub.7 can also be written into that identified word as well as having the contents of that selected word outputted to data bus 15 lines D.sub.0 -D.sub.7.
In memory 12, to transfer all the data stored in one line of the memory cell assembly 21 (i.e., 64 bits) to another line in memory 12 or into another memory, the procedure is as follows:
(i) Line decoder 22 identifies the line from which the data are to be transferred.
(ii) Using control line 13, the data in the selected line are outputted to the data bus 15 8-bit word by 8-bit word, with the words being sequentially selected by the column decoders 23.
(iii) If the memory line to which data are transferred is in another memory, the data outputted to data bus 15 are transferred to the data bus for the other memory and written into that other memory word-by-word. If the memory line to which data are transferred is in the same memory, the data applied to data bus 15 are then stored in a register (not shown) word-by-word and are later written from that register back into the memory at the new line, again word-by-word.
As is evident, the conventional data transferring method described above is inefficient when the total amount of the data to be transferred has more bits than the width of the data bus, the data bus width typically being the same size as a memory word. In such a case, transferring the data word-by-word is slow. Therefore, the conventional data transferring method suffers in that it takes a relatively long period of time to transfer a large quantity of data between memory lines or rows. Such transfer occurs often, for example, when a word processor transfers sentences of text.
In view of the foregoing, an object of this invention is to provide a data transferring method in which data can be transferred quickly.